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GCSE Computer Science · Revision

Fetch–decode–execute cycle

Step through a real program one transfer at a time. Watch the address in the Program Counter go out to RAM and come back as an instruction, then see how the CPU decodes and carries it out.

Central Processing Unit (CPU) In this simple view the Control Unit decodes each instruction. AddressBus DataBus ControlBus Program Counter 0000 0 Memory AddressRegister 0000 0 DECODE UNIT OPCODEOPERANDINSTRUCTION Accumulator 0000 0000 0 Arithmetic LogicUnit Memory DataRegister 0000 0000 0 Current InstructionRegister 0000 0000 opcode · operand Cache Small, fast memory inside the CPU for frequently used instructions and data. (Not used in this model.) ControlUnit Signal: — Cycle 1 Main Memory (RAM) Address Data
Address Data or instruction Control signal Click any RAM row to change it. → next step · ← back